Image Mosaic processor requirements
With the pixel pitch of the LED display getting smaller and the viewing distance getting closer, in order to achieve excellent display effect, not only requires the LED display itself to improve on the image processing and assembly process, but also puts forward higher requirements for the image splicing processor (hereinafter referred to as the splicer) at the front end of the LED display:
(1) Verify the synchronization of the output to avoid the phenomenon of unsynchronization of the splicing screen; (2) Optimize the image processing algorithm, so that the zoom processing of the image to maintain high definition; (3) Customize the output resolution to deal with the irregular physical resolution of the LED display.
Splicing processing technology for small pitch LED display
A key application of the splicer is that it can output multiple DVI signals and splice multiple displays arranged in a matrix to make it a complete display area logically. For LED display, we can define the display area driven by an LED controller as an independent LED display. The current LED controller uses DVI/HDMI as the signal input interface, supporting a maximum input resolution of 1920×1200@60Hz and a maximum bandwidth of 165MHz. The maximum physical resolution of the driven LED display is 1920×1200. As the display area of LED small pitch products is getting larger and larger, dozens of square meters of projects are common, the physical resolution of LED display is often more than 1920×1200, that is, each large LED display is composed of a number of independent display areas driven by a number of LED controllers, for the application of splicer, It is only necessary to provide a number of DVI output interfaces corresponding to the number of LED controllers, and the entire LED screen can be spliced. Splitter In the application of small-pitch LED display, there are several key technologies worth paying attention to: (1) signal output synchronization Splitter multi-channel DVI signal output, there is inevitably a signal synchronization problem. The asynchronous signal is output to the LED display, and the picture tearing phenomenon will appear at the splice, which is especially obvious when playing high-speed moving images. How to ensure the output synchronization of the signal becomes the key to measure the success or failure of a splicing system. (2) Graphics processing algorithm We know that the point-to-point image display effect is the best, after the reduction of the image, if only the use of ordinary graphics processing technology or general FPGA graphics processing algorithm, the edge of the image will appear jagged, and even pixels will be missing, the brightness of the image will decline. The high-end image processing chip or the FPGA system using complex graphics processing algorithms will maximize the display effect of the reduced image. Therefore, a good graphics processing algorithm is a key technology for a splicer applied to a small-pitch LED display. (3) The output small pitch LED display with non-standard resolution is composed of a matrix of display units of the same specifications, and the size and physical resolution of each display unit is fixed, but the entire large screen is spliced together, often not a standard physical resolution. For example, the resolution of the display unit is 128×96, which can only spell 1920×1152, but cannot spell 1920×1080. In a very large scale splicing system, the LED display area driven by each LED controller may not be the standard resolution, at this time, the splicing device has a non-standard resolution output is key, it can help us quickly find the right splicing method, so as to allocate resources reasonably, effectively save the use of LED controller and transmission equipment. At present, the splicer can be divided into four categories, namely, embedded pure hardware architecture, PCI-E bus architecture, distributed network architecture, and hybrid architecture. (1) Embedded pure hardware architecture The whole machine structure usually adopts the design of “backplane + signal acquisition board + main control board + signal output board”. The signal acquisition board performs signal processing work such as video acquisition, scaling, superposition and format conversion, and transmits the processed signals to the FPGA signal processing system of the main control board through the backplane bus. Through the embedded ARM system, the main control FPGA configuration, communication with the upper PC, data exchange between the system and other functions are realized, and the signal is output to the display terminal through the signal output board. The structure of the pure hardware architecture splicer is relatively simple, and it is not easy to have system failure. Acquisition board and output board can be hot-swappable, easy to replace; It can realize the acquisition and processing of multi-channel and multi-format signals. Backplane switching technology and output board unified clock technology ensure the synchronization of multi-channel signal output. The resolution of each DVI output signal can be customized, in line with the splicing characteristics of the LED display. Many features make the pure hardware architecture quickly become one of the mainstream products in the field of today’s splicer. However, due to the use of FPGA as the core image processing unit, the quality of the algorithm determines the quality of a splicer processing effect, especially the image scaling algorithm, how to optimize to achieve a clearer display effect has become an important indicator to determine the value of pure hardware splicer products. (2)PCI-E bus architecture Usually the splicer of the bus architecture uses PCIExpress technology, and the available data bandwidth is up to hundreds of Gbps. The host is equipped with high-performance CPU and large memory, and can preinstall different operating systems (such as 64-bit Windows7) according to different application fields, and can directly run various applications. The splicer is equipped with multiple high-performance graphics output cards, each with ultra-high internal bandwidth and video memory, and all output images are synchronized to eliminate image tearing between display units. At the same time, it is equipped with multiple input cards, supporting a variety of signal formats, and can perform image processing on input signals. PCI-E bus architecture splicer is a high-performance computer, all components are selected from the most advanced and mature technology of major hardware manufacturers, such as CPU can choose Intel, graphics card can choose Nvidia. All the high technology in the computer field can be quickly integrated. This makes the PCI-E bus architecture splicer has incomparable advantages in computing speed, image processing, operation mode and so on. PCI-E bus architecture splicer threshold is very low, for simple applications, an industrial computer, coupled with a professional multi-channel output graphics card can be achieved. On the other hand, how to solve the problem of system stability, how to design an intuitive and powerful control software, how to solve various problems of data transmission under high bus bandwidth, etc., all need a strong R & D team and a strong financial base, and the accumulation of experience. That is to say, the high-end PCI-E bus architecture splicer not only needs to meet the most basic applications such as signal acquisition, processing, splicing, but also needs more investment in the design of system stability, software ease of use, etc., in order to make the splicer meet a variety of harsh application environments. However, it should be noted that the bus architecture splicer mostly uses the Windows operating system, and once it is attacked by a virus, the system may be paralyzed and the display will stop. Moreover, due to the use of customized graphics cards, the resolution of each output channel generally needs to comply with VESA(Video Electronics Standards Association) standards, and non-standard resolution output cannot be defined, nor can different resolutions be defined for each channel. (3) Distributed network architecture The distributed network architecture splicer usually adopts a node-type hardware structure, each input and output nodes are independently separated, and the data is interactively transmitted through the twisted pair access central switch. Its core is a set of advanced video codec technology. Through various signal input nodes, the collected DVI, VGA, YPbPr, CVBS, 3G-SDI and other signals are processed and encoded. Through a dedicated network communication protocol, the encoded video is transmitted through the central switch to the output node for decoding. And converted to DVI digital signal output to the display terminal. The synchronization of output nodes becomes the key to the application of this system. One way is to send the synchronization code directly through the network to realize the synchronous output of multiple output nodes. However, due to the existence of the network bit error rate, after running this way for a period of time, there will still be output asynchronization. Another method is to physically connect multiple output nodes through the SYNC interface, select one output node as the host, and actively send synchronization codes to other output nodes, so that all output nodes receive synchronization signals at the same time, and realize true frame synchronization output, ensuring that the display image is complete and there is no tear at the screen splicing. At present, the application of distributed network architecture splicing system is more and more, because of its distributed characteristics, it is convenient for the integrated wiring in the whole building and the centralized management of multiple display terminals in different areas. With the help of advanced visualization software, it can provide users with humanized, visual and integrated services. However, limited by bandwidth and codec technology, distributed network architecture does not support dual-link DVI digital signal and HDMI signal access at present. At the same time, frame cache is needed in coding, processing, decoding and signal synchronous output, so there is a gap in real-time data compared with other splicing technologies. In addition, when more than 1920×1200 resolution images need to be displayed (more than two signal input nodes are required), it is impossible to guarantee the resynchronization output of the input signal from the multi-channel synchronization source. (4) Hybrid architecture Hybrid architecture generally refers to the combination of two or more of the above three splicing technologies or splicing systems. For example, PCI+ hardware backplane bus architecture splicer, its system control and image processing are independently realized. PCI bus is responsible for system control and running the operating system in the background; The hardware backplane bus is responsible for video image processing, and the system allows simultaneous processing of a large number of high-resolution input signals while still maintaining real-time operational performance and optimal image quality at full frame rates, while ensuring synchronization of the output signals. For important emergency sites, you can ensure that the screen is never black, even if the PCI bus is responsible for the operating system failure or virus infection, through the dedicated backplane graphics processing bus, you can ensure that foreign video images are displayed at any time. Through the hybrid architecture, it can be applied comprehensively, learn from each other, and greatly increase the stability of the system. This is also the development direction of splicing technology in the future, with a broader application space.
Application of small pitch LED display
At present, the application of small-pitch LED display is very wide, including but not limited to:
Military exercise command system
Public safety display command system
Power dispatching system
Traffic network and aviation monitoring display system
Production scheduling system for energy industry
Government, enterprises and institutions conference display system
Radio and television media display system
Public place information release system
